1. Field of the Invention
This invention relates to a digital interface. More particularly, it relates to an improved digital interface for an AC ""97 controller having expandable and automatic capabilities including effectively increased bus width, accessibility by a plurality of processors, and automatic creation of tag bits.
2. Background of Related Art
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a xe2x80x9ccodec.xe2x80x9d A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from digital signals, e.g., Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony, and were not capable of handling modem inputs. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo with processors having a 20-bit data bus) for higher quality use beyond that required for telephony. With higher quality and broader bandwidth capability, today""s codecs find practical application with consumer equipment such as voice band modems.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. One major step toward achieving this high S/N ratio was accomplished more recently by separating the conventional codec into two individual sub-systems: a controller sub-system or integrated circuit (IC) handling primarily the digital interface to a host processor, and an analog sub-system or IC handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented recently as the xe2x80x9cAudio Codec ""97 Component Specificationxe2x80x9d, Revision 1.03, Sep. 15, 1996; and the xe2x80x9cAudio Codec ""97xe2x80x9d, Revision 2.0, Intel Corporation, Sep. 29, 1997, (collectively referred to herein as xe2x80x9cthe AC ""97 Specificationxe2x80x9d). The AC ""97 Specification, i.e., both Revision 1.03 and 2.0 in their entirety are expressly incorporated herein by reference.
FIG. 5 shows a conventional split-architecture audio codec such as that defined by the AC ""97 Specification interfacing to an analog device, e.g., to a modem 510.
In particular, an AC controller sub-system 500 interfaces to an AC analog sub-system 502 via a five-wire time division multiplexed (TDM) bus referred to as the AC link 504a, 504b. The five-wire TDM bus of the AC link 504a, 504b comprises a sync signal 512, a reset signal 520, a serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 to the AC analog sub-system 502, a bit clock signal BIT_CLK 514, and a serial TDM data stream SDATA_IN 518 from the AC analog sub-system 502 to the AC controller 500. The bit clock signal BIT_CLK 514 is typically derived from an external crystal 508.
The circuitry in the conventional AC analog sub-system 502 which interfaces to an external analog device typically includes an analog-to-digital converter (ADC) 522 and a digital-to-analog converter (DAC) 524. The ADC 522 samples the analog signal input to the AC analog subsystem 502 and provides 16-, 18- or 20-bit data at 48 Ks/s to the AC link 504b for insertion into, e.g., time slot 5 of the serial TDM data stream SDATA_IN 518 to the AC controller sub-system 500. Conversely, the DAC 524 receives 16-, 18- or 20-bit data from the serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 and converts the same into an output analog signal, e.g., output to the low-speed voice band modem 510.
Conventional demodulation and modulation techniques such as quadrature amplitude modulation (QAM) or Carrierless Amplitude and Phase (CAP) may be performed by a digital signal processor (DSP) and/or other processor in conjunction with the ADC 522 and DAC 524.
FIG. 6 depicts a conventional sync or frame signal 512, serial TDM data stream SDATA_OUT 516, and serial TDM data stream SDATA_IN 518, in a twelve slot (plus slot 0) TDM bi-directional data stream between the analog and controller sub-systems 502,500 of a split-architecture audio codec such as in accordance with the AC ""97 Specification. The twelve time slots 1 to 12 of the serial TDM data streams SDATA_OUT 516 and SDATA_IN 518 are framed by the sync signal 512, which is derived from a TAG Phase 600 during time slot 0.
The TAG Phase 600 contains 16 bits, bit 0 of which corresponds to the presence of active data in any of time slots 1 to 12, and bits 1 to 12 which correspond respectively to the presence of active data in time slots 1 to 12, respectively. Bits 13 to 15 of the TAG Phase 600 are currently undefined in the AC ""97 Specification.
Time slots 1 and 2 of the serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 to the AC analog sub-system 502 comprise command addresses 601 and command data 602. Status addresses 621 and status data 622 are passed in time slots 1 and 2 of the serial TDM data stream SDATA_IN 518 from the AC analog sub-system 502 to the AC controller sub-system 500. Time slots 3 and 4 of the serial TDM data stream SDATA_OUT 516 and serial TDM data stream SDATA_IN 518 comprise the stereo pulse code modulated (PCM) audio data between the AC analog sub-system 502 and the AC controller sub-system 500. Time slot 5 of the serial TDM data stream SDATA_IN and SDATA_OUT 518, 516 conventionally contains the data from and to the low speed voice band modem 510 (FIG. 5). Time slot 6 of the serial TDM data stream SDATA_IN 518 contains microphone PCM data. The remaining time slots 7 through 12 of both the serial TDM data stream SDATA_IN and SDATA_OUT 518, 516 and time slot 6 of the serial TDM data stream SDATA_OUT 516 are unused in the conventional split-architecture audio codec.
The active status of TAG bits are conventionally written to once each frame by the processor in the AC controller sub-system 500. All time slots (i.e., slots 1--12) are 20 bits wide with the exception of the TAG phase 600 in slot 0, which is 16 bits wide.
FIG. 7 depicts in more detail the serial TDM data stream SDATA_OUT 516 with reference to the sync signal 512 and the bit clock signal BIT_CLK 514 in the current implementation of the AC ""97 Specification. The conventional bit clock signal BIT_CLK 514 is a fixed 12.288 MHz clock signal derived in the clock 506 from the external 24.576 MHz crystal oscillator 508 (FIG. 5).
Conventional AC ""97 split-architecture systems accommodate only one processor, treating the AC ""97 link as a single device to be used by only one processor. However, it has been appreciated by the present inventor that more recent applications would benefit from access to the AC ""97 link and the AC ""97 Analog sub-system by a plurality of processors, either all within the AC controller sub-system 500 and/or external to the AC controller sub-system 500. There is thus a need for an interface in an AC controller system which can provide access to the AC ""97 link and AC ""97 Analog sub-system by any of a plurality of processors.
Moreover, conventional data buses for suitable processors in an AC controller sub-system 500 generally include a standard 16-bit data bus. However, many of the components and corresponding time slot registers in the AC ""97 system are capable of use with more accuracy than 16 bits, e.g., with 20 bits. Conventionally, when a 16 bit data bus is utilized in an AC ""97 device, the least significant 4 bits in the 20 bit registers in the AC controller sub-system and/or AC analog sub-system are filled with zeroes to left-justify the available 16 bit data in a 20 bit register. Thus, the increased accuracy provided by the 20-bit capability of the AC ""97 Specification may not be fully utilized. Thus, there is a need for a method and apparatus which allows efficient use of the 20 (or more) bit capability of an AC ""97 Analog sub-system with data transfers limited to a data bus smaller than the general register width in the AC ""97 link.
Lastly, the TAG phase in the AC link""s data stream is updated each frame (e.g., at a rate of 48 KHz). As discussed, bit 0 of the TAG Phase 600 indicates whether any of slots 1-12 contain active data, and bits 1-12 indicate whether or not a corresponding slot 1-12 contains active data. Typically a processor in a conventional AC controller sub-system is saddled with the task of assembling the appropriate bits of the TAG phase and all at once writing to a register corresponding to data sent in time slot 0 once each frame. This task consumes a significant amount of processing time and requires prioritized action by the processor each frame. There is thus a need for a method and apparatus which automates the creation of the TAG Phase 600 to free the processor to handle other tasks.
In accordance with the principles of the present invention, a device for allowing a plurality of processors access to a common digital serial interface comprises a first write direction data bus corresponding to access to the digital serial interface from a first processor, and a second write direction data bus corresponding to access to the digital serial interface from a second processor. A first data register is in communication with the first write direction data bus, and a second data register is in communication with the second write direction data bus. A multiplexer is adapted to select one of the first data register and the second data register for output to the digital serial interface. A configuration register controls the multiplexer.
A method of providing a plurality of processors access to a plurality of time slots of a common digital serial interface in accordance with the present invention comprises providing a first write direction data bus for accessing the common digital serial interface from a first processor. A second write direction data bus is provided for accessing the common digital serial interface from a second processor. The first write direction data bus and the second write direction data bus are multiplexed between on a time slot-wise basis for output to the common digital serial interface.